In the semiconductor industry, there is a continuing desire for increased performance. In particular, the speed at which a particular circuit can transfer data or perform calculations is very important and often determines the circuit's marketability and appeal. Thus, any circuit which operates at an increased speed is very valuable.
Referring to FIG. 1, a conventional CMOS buffer circuit 10, shown as part of a CMOS NOR gate 11, is configured as a sense amplifier. A plurality of input signal lines A.sub.0 -A.sub.n are coupled to input node A via N-channel MOS pull-down transistors MN.sub.0 -MN.sub.n, respectively. A P-channel MOS "weak" pull-up transistor MP.sub.1 is connected between the voltage supply V.sub.DD and input node and, having its gate connected to ground potential, remains in a conductive state. Buffer/driver 12 receives a signal at node A and, in response thereto, drives output terminal Z. Capacitor C.sub.o models the capacitive nature of a load connected to circuit 10 at output terminal Z.
If all input signals A.sub.0 -A.sub.n are logic low, none of pull-down transistors MN.sub.A0 -MN.sub.An will conduct. Current flow through transistor MP.sub.1 will thus charge node A to approximately V.sub.DD, thereby pulling node A high. If, on the other hand, one or more of input signals A.sub.0 -A.sub.n is logic high, then one or more of associated pull-down transistors MN.sub.A0 -MN.sub.An will conduct and, in discharging node A, will pull node A low. In order to be consistent with CMOS levels and to ensure compatibility between buffer circuit 10 and other CMOS logic circuits, the signal swing of output terminal Z, and thus node A, should be approximately from ground to V.sub.DD, where V.sub.DD is 3.3 volts.
Charging and discharging node A between zero and 3.3 volts in order to effect logic transitions results in buffer circuit 10 having undesirably limits the switching speed of circuit 10. Further, noting that each of pull-down transistors MN.sub.A0 -MN.sub.An capacitively loads node A, increasing the number of input signals A coupled to circuit 10 via pull-down transistors MN.sub.A increases the capacitance between node A and ground and, therefore, necessarily decreases the switching speed of circuit 10. The capacitive load at node A thus requires an undesirable balancing between speed and signal handling capability.